1. Field of the Invention
Apparatuses and method consistent with the present invention relate to reading data, and more particularly, to capturing data by using a data transition of a data signal.
2. Description of the Related Art
Most digital devices today use low-cost Synchronous Dynamic Random Access Memory (SDRAM) as their main storage device. The greater number of SDRAM usage led to a greater capacity of SDRAM, which in turn led to a realization of high-speed actions. Thus, necessary timing for input/output (I/O) has become a very important issue.
When reading data, related art SDRAMs transmit data signals DQ and data strobe signals DQS of identical phase to hosts.
Thus, most controllers shift the data strobe signals DQS by 90° or 120° to delay the data strobe signals DQS. Then, the controllers directly capture the read data from SDRAM by using the delayed data strobe signals DQS as a trigger.
Such methods are used for disposing the transition of the data strobe signals DQS at a center between the transitions of the read data. This allows an equal division of setup margin and hold margin of the data signals DQ produced by the data strobe signals DQS, providing maximum margin for both transitions.
The setup margin indicates a time margin between a time point where data transition, that is, a status transformation of data, is generated and a point where a reading operation is generated. The hold margin refers to a time margin between a point where data is read and a point where the next state transformation of data takes place.
The reason behind the maximum procurement of the setup margin/hold margin of the read data is to prevent interference to the reading process caused by instantaneous noise due to an unstable routing path entering a flip-flop (F/F) through I/O from a pin.
To use the conventional technology, as described in FIG. 1, a delicate delay line, and a clock synchronizing module such as a delay locked loop (DLL) that produces a 90° or 120° delay by measuring a period of an external data strobe signal or a clock (CLK) are necessary for delaying the data strobe signal DQS.
FIG. 1 is a block diagram illustrating a general data strobe signal DQS control device for reading external data, according to a conventional technology.
Referring to FIG. 1, the general data strobe signal DQS control device comprises a delay locked loop (DLL) 110, a control unit 120, a delay line 130, and a flip-flop (F/F) 140.
General data strobe signal DQS control devices may be included in a memory controller. External data signals DQ and data strobe signals DQS are generally transmitted to a memory controller from SDRAM at identical phases.
Thus, memory controllers use the data strobe signals DQS to latch the transmitted external data signals. The data strobe signals have identical phase as external data signals. Therefore, data strobe signal DQS control devices shift the data strobe signals DQS for certain time period and latch the external data with the data strobe signals that have been shifted. For example, in a read process of double data rate (DDR) SDRAM, the data strobe signals DQS must be shifted by 90° to optimize the setup margin and holdup margin of the data.
The DLL 110 receives a system clock or a data strobe signal DQS from an external source, measures a period of the received system clock or data strobe signal DQS, and outputs the measured periods. The output of the DLL 110 may be represented in the unit of the number of delay chains included in the DLL 110, that is, as the number of taps.
The control unit 120 receives the period of the system clock or the data strobe signal DQS from the DLL 110 and determines the delay length of the data strobe signal DQS to optimize the setup margin and hold margin of the data. For example, a 90° delay is adequate for DDR SDRAMs. In such a case, the DLL 110 counts the number of delay chains regarding 1 cycle (360°) of the data strobe signal DQS and the control unit 120 multiplies the number of delay chains regarding 1 cycle by ¼ to compute the number of delay chains required for the 90° shift of the data strobe signal DQS.
The delay line 130 delays the data strobe signal DQS according to the delay length determined by the control unit 120.
The flip-flop (F/F) 140 latches external data by using the system clock or data strobe signal that has been output after being delayed at the delay line 130 as a trigger signal, and outputs the read data.
FIG. 2 is a time graph illustrating capturing of data signals by using delayed data strobe signals DQS. FIG. 3 is a diagram illustrating a skew generated from data signals DQ and data strobe signals DQS.
Referring to FIG. 2, data reading executed through the device of FIG. 1 is illustrated in a time graph. As illustrated in FIG. 2, a data strobe signal DQS that is delayed by 90° is used as a trigger signal to capture the data signal DQ at a point where the data strobe signal undergoes transition.
However, as can be seen in FIG. 3, skews may be generated among data signals DQ or among a data signal DQ and a data strobe signal DQS. Skews generated from routing among a data signal DQ and a data strobe signal DQS are usually caused by instability of I/O voltage or cross-talk among bits. Therefore, skews generating from the internal signals may cause a transformation of setup margin/hold margin of data, and thereby make the reading process unstable.
Referring back to FIG. 2, dot-lined zone 210 illustrates a failed data capture. When using a data strobe signal DQS that is delayed by 90° as a trigger, skew is generated in the data signal DQ as shown in the dot-lined zone 210, causing a worsening of the margin. This in turn causes a failure in capturing the data signal DQ at an accurate timing.
Locking of a margin resulting from skews among data signals DQ or skews among a data signal DQ and a data strobe signal DQS during a data reading is essential; however, locking of a clock or a data strobe signal occurs at an idle state of the system. Therefore, the methods described above can be disadvantageous for not being able to lock the worsening of margins in real time.
Furthermore, in actual chips, skews among data signals DQ resulting from fluctuations in a power level, fluctuations in a reference voltage (VREF), skews among routing, or cross-talks of a data signal occur frequently, and the numerical values of the skews fluctuate frequently.
The skews generated in the methods described above worsen the setup margin or hold margin of the flip-flop of a controller interface. When data transition rate increases, the skews also become greater due to increased instability of I/O voltage level and influences of cross-talk among data.
Therefore, if skews among data bits or skews among a data strobe signal DQS and a data signal DQ change drastically, it becomes very difficult or impossible to increase the setup margin and hold margin of all data bits to their maximum, regardless of the delay location of the data strobe signals DQS.
Furthermore, when the clock's duty ratio changes due to jitters of the clock signal, a duty ratio of the data strobe signals DQS also changes, causing a problem even where the data strobe signal is delayed by 90° or 120°.
In addition, a measurement of a delay length of 90° or 120° of the data strobe signal DQS is a value set by only measuring a period of the clock or data strobe signal DQS. Thus, skews among data signals DQ, skews among data signals DQ and clock, or skews among data signals DQ and data strobe signals DQS cannot be measured, thereby causing a problem.